Frequency synthesizers can be used in particular in wireless communication systems, or, more generally, in telecommunications systems. These frequency synthesizers supply high frequency signals within a determined frequency band so as to cover a telecommunication band, such as the American ISM band (902 to 928 MHz) for example. In order to obtain the desired output frequency at the voltage controlled oscillator output, a binary selection signal, provided by the mode selection means, commands a series of selected modes in the divider circuit in a determined order. In a first mode M1 equal to 0, the output signal frequency of the voltage controlled oscillator is divided by a first division factor of the divider circuit, whereas in a second mode M2 equal to 1, a division is carried out by a second division factor of the divider circuit.
When a synthesizer output signal frequency close to the centre of the frequency band is selected, problems are generally encountered linked with parasitic or interference from low frequency transmissions or components. These parasitic transmissions can disturb the synthesizer output signal. The same is true for a frequency selected at the low and high limits of the synthesizer frequency band, but generally the synthesizer is provided with a larger frequency bandwidth than the communication frequency band. Consequently, problems of parasitic transmissions essentially concern the centre of the band.
Problems of parasitic low frequency transmissions mainly occur in the series of modes in time carried out via the programmed mode selection means, which may preferably be a sigma-delta type modulator. A modulator of the sigma-delta type defines a series of modes in accordance with a pseudo-random configuration in a binary selection signal controlling the divider circuit. This mode equals 0 and mode equals 1 series is dependent upon a programming signal received from the selected frequency of the voltage controlled oscillator output signal.
For this type of sigma-delta modulator, normally the mode equals 1 and mode equals 0 variation in the mode series is at a higher frequency than the low-pass filter cut-off frequency. This allows noise to be pushed towards the high frequencies, which are filtered. However, for a programmed output signal frequency close to the centre of the band, the mode equals 0 number is substantially equal to the mode equals 1 number. Depending upon the periodicity of 0 and 1 in the binary signal mode series, a 1 may sometimes occur in place of a 0, or a 0 in place of a 1. This results in a low frequency at each occurrence of 1 or 0 in the mode series over time. These rare occurrences of 1 or 0 in the binary signal mode series are thus not filtered by the low-pass filter, which disturbs the voltage controlled oscillator.
These problems of parasitic low frequency transmissions are the same for an output signal frequency that is chosen at the bottom or top limit of the frequency band. In such case, a 1 might rarely occurs among all the 0s of the mode series for a frequency at the bottom limit of the frequency band, or rarely a 0 among all the 1s for a frequency at the top limit of the frequency band. However, since the determined frequency band of the frequency synthesizer is generally broader than the telecommunications frequency band, a frequency close to the bottom and top limits of the frequency band will never be programmed. Consequently, the main problem of parasitic transmissions relates to the programming of a voltage controlled oscillator frequency close to the centre of the frequency band.
In order to try to reduce problems linked to parasitic low frequency components, it is known to inject random noise into the sigma-delta type phase-lock loop. However, this practice has the drawback of only partially suppressing these parasitic or interfering components, and also has the drawback of adding broadband noise to the useful frequency synthesizer signal.
A noise reduction frequency synthesizer is known from US Patent No. 2003/0227301. This frequency synthesizer is based on a conventional phase-lock loop (PLL), and the use of a sigma-delta modulator, which selects the division ratio of a multi-mode divider. One object of this synthesizer is to resolve the problem of dead bands, when the division factor is chosen to be equal to N or N+1. This synthesizer thus includes a first divider block for dividing the reference frequency of an oscillator, a second divider block for dividing, by a selected factor, the frequency of the high frequency signals of a voltage controlled oscillator, and a division ratio controller having a sigma-delta modulator. The second divider block divides the frequency of the high frequency signals by a first factor N or by a second factor N+1 or by a third factor N+2. Selection of the division factor is performed as a function of a selection signal provided by the sigma-delta modulator combined with a mode controller. Owing to a succession of modes over time between the three division factors that can be selected, it is possible to reduce the quantification noise.
However, configuring this frequency synthesizer in order to remove parasitic transmissions or components for a programmed frequency of an output signal close to the centre of the synthesizer frequency band is not envisaged. Moreover, mode switching is carried out over time by continuously using three division factors of the second divider block, which is thus controlled by 2 bit selection signals, which consumes a large amount of electric energy and is relatively complicated to implement.